| AMD Zen+ | |
| Produced-Start: | April 2018 |
| Designfirm: | AMD |
| Manuf1: | GlobalFoundries |
| Cpuid: | Family 17h |
| L1cache: | 64 KB instruction, 32 KB data per core |
| L2cache: | 512 KB per core |
| L3cache: | 8 MB per (APU: 4 MB) |
| Size-From: | 12 nm (FinFET) |
| Transistors1: | 4.8 billion per 8-core "Zeppelin" die |
| Arch: | AMD64 (x86-64) |
| Sock1: | Socket AM4 |
| Sock2: | Socket TR4 |
| Brand1: | Ryzen |
| Brand2: | Ryzen Threadripper |
| Brand3: | Athlon |
| Pcode1: | Pinnacle Ridge (Desktop)[1] |
| Pcode2: | Colfax (HEDT) |
| Pcode3: | Picasso (APU/Embedded) |
| Predecessor: | Zen (1st gen) |
| Successor: | Zen 2 |
| Support Status: | Supported |
Zen+ is the name for a computer processor microarchitecture by AMD. It is the successor to the first gen Zen microarchitecture,[2] and was first released in April 2018,[3] powering the second generation of Ryzen processors, known as Ryzen 2000 for mainstream desktop systems, Threadripper 2000 for high-end desktop setups and Ryzen 3000G (instead of 2000G) for accelerated processing units (APUs).
Zen+ uses GlobalFoundries' 12 nm fabrication process,[4] an optimization of the 14 nm process used for Zen, with only minor design rule changes.[5] This means that the die sizes between Zen and Zen+ are identical as AMD chose to use the new smaller transistors to increase the amount of empty space, or "dark silicon", between the various features on the die. This was done to improve power efficiency & reduce thermal density to allow for higher clock speeds, rather than design an entirely new floorplan for a physically smaller die (which would have been significantly more work and thus more expensive).[6] These process optimizations allowed 12 nm Zen+ to clock about +250 MHz (≈6%) higher, or to lower power consumption when at the same frequency by 10%, when compared to their prior 14 nm Zen products.[7] Although conversely at the microarchitecture level, Zen+ had only minor revisions versus Zen. Known changes to the microarchitecture include improved clock speed regulation in response to workload ("Precision Boost 2"),[8] reduced cache and memory latencies (some significantly so), increased cache bandwidth, and finally improved IMC performance allowing for better DDR4 memory support (officially JEDEC rated to support up to 2933 MHz compared to just 2666 MHz on the prior Zen core),[9] and fixed many hardware bugs found on Zen 1, such as fTPM / PSP bugs on Zen 1, and SVM / SLAT bugs on Zen 1.
Zen+ also supports improvements in the per-core clocking features, based on core utilization and CPU temperatures. These changes to the core utilization, temperature, and power algorithms are branded as "Precision Boost 2" and "XFR2" ("eXtended Frequency Range 2"), evolutions of the first-generation technologies in Zen. On Zen, XFR gave an additional 50 to 200 MHz clock speed increase (in 25 MHz increments) over the maximum Precision Boost clocks. For Zen+, XFR2 is no longer listed as a separate clock modifier. Instead, the XFR temperature, power, and clock monitoring and logic feeds into the Precision Boost 2 algorithm to adjust clocks and power consumption opportunistically and dynamically.[10] [11]
Ultimately, the changes in Zen+ resulted in a 3% improvement in IPC over Zen; which in conjunction with 6% higher clock speeds resulted in up to 10% overall increase in performance.
APU features table
In 2022, AMD announced the R2000 series of embedded APUs.[12]