3 nm process explained

In semiconductor manufacturing, the "3 nm" process is the next die shrink after the "5 nm" MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its "3 nm" gate all around (GAA) process, named "3GAA", in mid-2022. On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its "3 nm" semiconductor node ("N3") was under way with good yields. An enhanced "3 nm" chip process called "N3E" may have started production in 2023.[1] American manufacturer Intel planned to start 3 nm production in 2023.[2] [3]

Samsung's "3 nm" process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's "3 nm" process still uses FinFET (fin field-effect transistor) technology,[4] despite TSMC developing GAAFET transistors.[5] Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[6] Intel's process (dubbed "Intel 3", without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement.[7]

Projected node properties according to International Roadmap for Devices and Systems (2021)
Node name Gate pitch Metal pitch Year
"5 nm"51 nm 30 nm 2020
"3 nm" 48 nm 24 nm 2022
45 nm 20 nm 2025
40 nm 16 nm 2027
The term "3 nanometer" has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "3 nm" node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.

However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[8] [9] There is no industry-wide agreement among different manufacturers about what numbers would define a "3 nm" node.[10] Typically the chip manufacturer refers to its own previous process node (in this case the "5 nm" node) for comparison. For example, TSMC has stated that its "3 nm" FinFET chips will reduce power consumption by 25–30% at the same speed, increase speed by 10–15% at the same amount of power and increase transistor density by about 33% compared to its previous "5 nm" FinFET chips.[11] [12] On the other hand, Samsung has stated that its "3 nm" process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous "5 nm" process.[13] EUV lithography faces new challenges at 3 nm which lead to the required use of multipatterning.[14]

History

Research and technology demos

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes.[15] [16] In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.[17]

Commercialization history

In late 2016, TSMC announced plans to construct a "5 nm"–"3 nm" node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.

In 2017, TSMC announced it was to begin construction of the "3 nm" semiconductor fabrication plant at the Tainan Science Park in Taiwan. TSMC plans to start volume production of the "3 nm" process node in 2023.[18] [19] [20] [21] [22]

In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out "3 nm" test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.[23]

In early 2019, Samsung presented plans to manufacture "3 nm" GAAFET (gate-all-around field-effect transistors) at the "3 nm" node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with "7 nm".[24] Samsung's semiconductor roadmap also included products at "8", "7", "6", "5", and "4 nm" 'nodes'.[25]

In December 2019, Intel announced plans for "3 nm" production in 2025.[26]

In January 2020, Samsung announced the production of the world's first "3 nm" GAAFET process prototype, and said that it is targeting mass production in 2021.[27]

In August 2020, TSMC announced details of its "N3" process, which is new rather than being an improvement over its "N5" process.[28] Compared with the "N5" process, the "N3" process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC was planning volume production in the second half of 2022.[29]

In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process (previously named Intel 7nm), the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.

In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers’ first "3 nm"-based chip designs in the first half of 2022, while its second generation of "3 nm" is expected in 2023.

In June 2022, at TSMC Technology Symposium, the company shared details of its "N3E" process technology scheduled for volume production in 2023 H2: 1.6× higher logic transistor density, 1.3× higher chip transistor density, 10-15% higher performance at iso power or 30-35% lower power at iso performance compared to TSMC N5 v1.0 process technology, FinFLEX technology, allowing to intermix libraries with different track heights within a block etc. TSMC also introduced new members of "3 nm" process family: high-density variant N3S, high-performance variants N3P and N3X, and N3RF for RF applications.[30] [31] [32]

In June 2022, Samsung started "initial" production of a low-power, high-performance chip using "3 nm" process technology with GAA architecture.[33] [34] According to industry sources, Qualcomm has reserved some of "3 nm" production capacity from Samsung.[35]

On 25 July 2022, Samsung celebrated the first shipment of "3 nm" Gate-All-Around chips to a Chinese cryptocurrency mining firm PanSemi.[36] [37] [38] [39] It was revealed that the newly introduced 3 nm MBCFET process technology offers 16% higher transistor density,[40] 23% higher performance or 45% lower power draw compared to an unspecified "5 nm" process technology.[41] Goals for the second-generation "3 nm" process technology include up to 35% higher transistor density,[40] further reduction of power draw by up to 50% or higher performance by 30%.[42] [40]

On 29 December 2022, TSMC announced that volume production using its "3 nm" process technology N3 is under way with good yields.[43] The company plans to start volume manufacturing using refined "3 nm" process technology called N3E in the second half of 2023.[44]

In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their "3 nm" process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm² for N3 and 0.021 μm² for N3E (same as in N5). For N3E process, depending on the number of fins in cells used for design, area scaling compared to N5 2-2 fin cells ranges from 0.64x to 0.85x, performance gains range from 11% to 32% and energy savings range from 12% to 30% (the numbers refer to Cortex-A72 core). TSMC's FinFlex technology allows to intermix cells with different number of fins in a single chip.[45] [46] [47] [48]

Reporting from IEDM 2022, semiconductor industry expert Dick James stated that TSMC's "3 nm" processes offered only incremental improvements, because limits have been reached for fin height, gate length, and number of fins per transistor (single fin). After implementation of features such as single diffusion break, contact over active gate and FinFlex, there will be no more room left for improvement of FinFET-based process technologies.[49]

In April 2023, at its Technology Symposium, TSMC revealed some details about their N3P and N3X processes the company had introduced earlier: N3P will offer 5% higher speed or 5%–10% lower power and 1.04× higher "chip density" compared to N3E, while N3X will offer 5% speed gain at the cost of ~3.5× higher leakage and the same density compared to N3P. N3P is scheduled to enter volume production in the second half of 2024, and N3X will follow in 2025.[50]

In July 2023, semiconductor industry research firm TechInsights said it has found that Samsung's "3 nm" GAA (gate-all-around) process has been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT.[51]

On 7 September 2023, MediaTek and TSMC announced that MediaTek have developed their first "3 nm" chip, volume production is expected to commence in 2024.[52]

On 12 September 2023, Apple announced the iPhone 15 Pro and iPhone 15 Pro Max would feature a "3 nm" chip, the A17 Pro.[53] One month later, on 30 October 2023, the "3 nm" process made it into the M3 chip family (M3, M3 Pro and M3 Max) which powers the MacBook Pro and iMac.[54]

"3 nm" process nodes

Samsung[55] [56] [57] [58] TSMC[59] Intel[60]
Process name3GAE
SF3E		3GAP
SF3		N3N3EN3PN3X3
Transistor typeMBCFETFinFET
Transistor density (MTr/mm2)150189.8[61] 197215.6[62] 224.2[63]
SRAM bit-cell size (μm2)0.01990.021
Transistor gate pitch (nm)404548
Interconnect pitch (nm)3223
Release status

Further reading

External links

Notes and References

  1. Web site: TSMC Exceeds 3nm Yield Expectations & Production Can Start Sooner Than Planned . Ramish Zafar . wccftech.com . 4 March 2022 . 19 March 2022 . 16 March 2022 . https://web.archive.org/web/20220316084750/https://wccftech.com/tsmc-exceeds-3nm-yield-expectations-production-can-start-sooner-than-planned/ . live.
  2. News: Gartenberg . Chaim . Intel has a new architecture roadmap and a plan to retake its chipmaking crown in 2025 . 22 December 2021 . . 26 July 2021 . 20 December 2021 . https://web.archive.org/web/20211220083235/https://www.theverge.com/2021/7/26/22594074/intel-acclerated-new-architecture-roadmap-naming-7nm-2025 . live .
  3. Web site: Intel Technology Roadmaps and Milestones. 17 February 2022. Intel. en. 16 July 2022. https://web.archive.org/web/20220716192641/https://www.intel.com/content/www/us/en/newsroom/news/intel-technology-roadmaps-milestones.html#gs.tuhd2s. live.
  4. Web site: Where are my GAA-FETs? TSMC to Stay with FinFET for 3nm. Dr Ian. Cutress. AnandTech. 12 September 2020. 2 September 2020. https://web.archive.org/web/20200902075730/https://www.anandtech.com/show/16041/where-are-my-gaafets-tsmc-to-stay-with-finfet-for-3nm. live.
  5. Web site: TSMC Plots an Aggressive Course for 3nm Lithography and Beyond – ExtremeTech. Extremetech.com. 12 September 2020. 22 September 2020. https://web.archive.org/web/20200922235956/https://www.extremetech.com/computing/314204-tsmc-plots-an-aggressive-course-for-3nm-lithography-and-beyond. live.
  6. Web site: Samsung at foundry event talks about 3nm, MBCFET developments. Techxplore.com. 22 November 2021. 22 November 2021. https://web.archive.org/web/20211122203559/https://techxplore.com/news/2019-05-samsung-foundry-event-3nm-mbcfet.html. live.
  7. Web site: Intel Updates IDM 2.0 Strategy With New Node Naming And Transistor And Packaging Technologies . 26 July 2021 . Patrick Moorhead . Forbes . 18 October 2021 . 18 October 2021 . https://web.archive.org/web/20211018091320/https://www.forbes.com/sites/patrickmoorhead/2021/07/26/intel-updates-idm-20-strategy-with-new-node-naming-and-technologies/?sh=59b7592729d5 . live .
  8. Web site: TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is" . Pcgamesn.co . 10 September 2019 . 20 April 2020 . 17 June 2020 . https://web.archive.org/web/20200617230408/https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers . live .
  9. A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric . Samuel K. Moore . IEEE . IEEE Spectrum . 21 July 2020 . 20 April 2021 . 2 December 2020 . https://web.archive.org/web/20201202002819/https://spectrum.ieee.org/semiconductors/devices/a-better-way-to-measure-progress-in-semiconductors . live .
  10. , according to which "There is not yet aconsensus on the node naming across different foundries and integrated device manufacturers (IDMs)".
  11. Web site: TSMC details its future 5nm and 3nm manufacturing processes—here's what it means for Apple silicon . Macworld . 25 August 2020 . Jason Cross . 20 April 2021 . 20 April 2021 . https://web.archive.org/web/20210420104726/https://www.macworld.com/article/234529/tsmc-details-its-future-5nm-and-3nm-manufacturing-processesheres-what-it-means-for-apple-silicon.html . live .
  12. Web site: The future of leading-edge chips according to TSMC: 5nm, 4nm, 3nm and beyond. Anton Shilov. Techradar.com. 31 August 2020. 20 April 2021. 20 April 2021. https://web.archive.org/web/20210420104725/https://www.techradar.com/news/the-future-of-leading-edge-chips-according-to-tsmc-5nm-4nm-3nm-and-beyond. live.
  13. Web site: Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture . 30 June 2022 . 8 July 2022 . 8 July 2022 . https://web.archive.org/web/20220708021931/https://news.samsung.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture . live .
  14. Web site: EUV's Pupil Fill and Resist Limitations at 3nm. Chen. Frederick. LinkedIn. 17 July 2022. https://web.archive.org/web/20220729121139/https://www.linkedin.com/pulse/euvs-pupil-fill-resist-limitations-3nm-frederick-chen. 29 July 2022.
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  16. Wakabayashi . Hitoshi . Yamagami . Shigeharu . Ikezawa . Nobuyuki . Ogura . Atsushi . Narihiro . Mitsuru . Arai . K. . Ochiai . Y. . Takeuchi . K. . Yamamoto . T. . Mogami . T. . IEEE International Electron Devices Meeting 2003 . Sub-10-nm planar-bulk-CMOS devices using lateral junction control . 2100267 . December 2003 . 20.7.1–20.7.3 . 10.1109/IEDM.2003.1269446. 0-7803-7872-5 .
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  18. Web site: TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report . Ramish . Zafar . Wccftech.com . 15 May 2019 . 6 December 2019 . 7 November 2020 . https://web.archive.org/web/20201107234628/https://wccftech.com/tsmc-2nm-research-taiwan/ . live .
  19. Web site: TSMC to start production on 5nm in second half of 2020, 3nm in 2022. Techspot.com. 8 December 2019 . 12 January 2020. 19 December 2019. https://web.archive.org/web/20191219211202/https://www.techspot.com/news/83080-tsmc-start-production-5nm-second-half-2020-3nm.html. live.
  20. Web site: Report: TSMC To Start 3nm Volume Production In 2022. Lucian. Armasu 2019-12-06T20:26:59Z. Tom's Hardware. 6 December 2019 . 19 December 2019. 15 September 2022. https://web.archive.org/web/20220915124610/https://www.tomshardware.com/news/report-tsmc-to-start-3nm-volume-production-in-2022. live.
  21. Web site: TSMC 3nm process fab starts construction - mass production in 2023. 25 October 2019. Gizchina.com. 12 January 2020. 12 January 2020. https://web.archive.org/web/20200112210328/https://www.gizchina.com/2019/10/25/tsmc-3nm-process-fab-starts-construction-mass-production-in-2023/. live.
  22. Web site: TSMC starts constructing facilities to turn out 3nm chips by 2023. Alan. Friedman. Phone Arena. 27 October 2019 . 12 January 2020. 12 January 2020. https://web.archive.org/web/20200112210316/https://www.phonearena.com/news/TSMC-starts-building-facilities-to-manufacture-3nm-chips_id119977. live.
  23. Imec and Cadence Tape Out Industry's First 3nm Test Chip . 28 February 2018 . . 18 April 2019.
  24. Web site: Samsung Unveils 3nm Gate-All-Around Design Tools - ExtremeTech. ExtremeTech. 22 July 2023.
  25. Web site: Samsung Announces 3nm GAA MBCFET PDK, Version 0.1. Ian. Cutress. AnandTech. 19 December 2019. 14 October 2019. https://web.archive.org/web/20191014033656/https://www.anandtech.com/show/14333/samsung-announces-3nm-gaa-mbcfet-pdk-version-01. live.
  26. Web site: Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm. Dr Ian. Cutress. AnandTech. 11 December 2019. 12 January 2021. https://web.archive.org/web/20210112092150/https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029. live.
  27. Web site: Samsung Prototypes First Ever 3nm GAAFET Semiconductor. Broekhuijsen 2020-01-03T16:28:57Z. Niels. Tom's Hardware. 3 January 2020 . en. 10 February 2020. 15 September 2022. https://web.archive.org/web/20220915124610/https://www.tomshardware.com/news/samsung-prototypes-first-ever-3nm-gaafet-semiconductor. live.
  28. Web site: TSMC: 3nm EUV Development Progress Going Well, Early Customers Engaged. Anton. Shilov. AnandTech. 12 September 2020. 3 September 2020. https://web.archive.org/web/20200903023151/https://www.anandtech.com/show/14666/tsmc-3nm-euv-development-progress-going-well-early-customers-engaged. live.
  29. Web site: TSMC roadmap update: N3E in 2024, N2 in 2026, major changes incoming. AnandTech. 22 April 2022. 12 May 2022. 9 May 2022. https://web.archive.org/web/20220509122111/https://www.anandtech.com/print/17356/tsmc-roadmap-update-n3e-in-2024-n2-in-2026-major-changes-incoming. live.
  30. Web site: TSMC Technology Symposium Review . SemiWiki . 22 June 2022.
  31. Web site: TSMC Readies Five 3nm Process Technologies, Adds FinFlex For Design Flexibility . AnandTech . 16 June 2022.
  32. Web site: N3E Replaces N3; Comes In Many Flavors . WikiChip Fuse . 4 September 2022.
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  35. Web site: Samsung Electronics begins 'trial production' of 3-nano foundry...The first customer is a Chinese ASIC company. TheElec. 28 June 2022. 28 July 2022. 28 July 2022. https://web.archive.org/web/20220728080413/https://www-thelec-kr.translate.goog/news/articleView.html?idxno=17300&_x_tr_sl=auto&_x_tr_tl=en&_x_tr_hl=en&_x_tr_pto=wapp. live.
  36. Web site: Samsung's 3nm trial production run this week to make Bitcoin miner chips. SamMobile. 28 June 2022. 27 July 2022. 27 July 2022. https://web.archive.org/web/20220727165146/https://www.sammobile.com/news/samsung-3nm-trial-production-run-this-week-make-bitcoin-miner-chips/. live.
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